In non-volatile semiconductor memory device, such as NAND flash memory, a plurality of memory cells which are connected in series form a memory cell unit, and the memory cell unit is connected between a bit line and a source line. A memory cell array is formed of a plurality of memory cell units. In each memory cell unit, data is written in memory cells in order from, for example, a memory cell which is closer to a source line.
In recent years, multi-level memories, in which a plurality of bits can be stored in a memory cell, have been developed. In multi-level memories, one of a plurality of threshold voltages is stored in a memory cell, and a distribution width of each threshold voltage is set narrower than binary memories. Therefore, when data is written in adjacent memory cells in a multi-level memory, the threshold voltage of a memory cell in which data has been written earlier than the adjacent memory cells is changed. This is the problem which multi-level memories have. In particular, when write data have regular bias, change in the threshold voltage increases.
Therefore, to avoid regular bias of write data, the write data is randomized in, for example, an external controller.